Multilevel-Cell Memory Structures Employing Multi-Memory Layers with Tungsten Oxides and Manufacturing Method

ABSTRACT

The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to high density memory devices based on programmable resistance memory materials, including metal-oxide based materials and other materials, and to methods for manufacturing such devices.

2. Description of Related Art

Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change.

Phase change based memory materials, like chalcogenide based materials and similar materials, can also be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.

The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause the transition of phase change material from the crystalline state to the amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element.

One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.

Problems have arisen in manufacturing such devices with very small dimensions, and with variations in process that meet tight specifications needed for large-scale memory devices. As demand for greater memory capacity is sought, a phase change memory that stores multiple bits per memory layer would be highly desirable.

SUMMARY OF THE INVENTION

The present invention provides multilevel-cell (MLC) memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states.

In a first embodiment, a multilevel-cell memory structure includes a first memory layer structure and a second memory layer structure. Each of the memory layer structures is physically and electrically connected to a bit line on top. The first or lower memory layer structure is connected to an n-p diode where the n-p diode is connected to a first bit line. The second or upper memory layer is connected to a p-n diode on the bottom where the p-n diode is connected to a second bit line. The second bit line is shared between the first memory layer structure and the second memory layer structure.

The second bit line is further connected to the first memory layer structure. Each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

The critical dimension of the tungsten oxide region is less than the size of the tungsten plug member. The critical dimension of the tungsten oxide region is also less than the size of the p-n diode. The relationship between the critical dimension of the tungsten oxide region, the critical dimension of the tungsten plug member, and the thickness of the p-n diode can be represented mathematically as follows: d_(A)≈d_(W)−2*t_(D), where the parameter d_(A) represents the critical dimension of the tungsten plug, the parameter d_(W) represents the critical dimension of the plug structure member, and the parameter t_(D) represents the critical dimension of the p-n diode. The critical dimension of the p-n diode is larger than the critical dimension of the tungsten oxide region, represented mathematically as d_(D)>d_(A).

In a second embodiment, a multilevel-cell memory structure comprises a first memory layer structure and a second memory layer structure. Each of the first and second memory layer structures includes a tungsten oxide region extending from a principle surface of a tungsten plug member where the outer surface of the tungsten plug member is surrounded by a barrier member. Each of the tungsten plug structures has a dimension that is sufficiently small so that a dielectric step during the manufacturing process can be skipped. The critical dimension for each tungsten plug structure is about the same size as the critical dimension for an active area (the tungsten oxide region).

In a third embodiment, a multilevel-cell memory structure comprises a first memory layer structure and a second memory layer structure. The first memory layer structure includes the tungsten oxide region, a tungsten plug structure having a first plug portion and a second plug portion, and the outer wall of the second plug is surrounded by a barrier member. The critical dimension of the first plug portion is similar to the critical dimension of the active area, i.e, tungsten oxide region. The tungsten oxide portion extends from a principle surface or a top surface of the first plug portion The first plug portion has a dimensional value which is less than the second plug portion. The first plug portion and the second plug portion in each memory layer structure can be manufactured using a self-align process or an non-self-align process.

A method for manufacturing a memory device is also described that comprises a plug structure with a plug material surrounded by a barrier material and disposed between dielectric members. The top portion of the plug material and the barrier material are etched with a dry etch using a first chemistry followed by a wet recess etch with a second chemistry. Dielectric spacers are formed over a principle surface of the etched plug material. A tungsten oxide region is formed that enters the principle surface of the etched plug material by a dry oxygen plasma strip. A bit line is formed into the dielectric spacers and over the tungsten oxide region.

Broadly stated, a memory structure having multiple memory layers comprises a first memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode and electrically connecting between the first electrode and a second electrode, the first electrode having a dimension that is substantially similar to a dimension of the tungsten oxide region; and a second memory layer structure, coupled to the first memory layer structure, having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode in the second memory layer structure and electrically connecting between the first electrode in the second memory layer structure and a second electrode in the second memory layer structure, the first electrode in the second memory layer structure having a dimension that is substantially similar to a dimension of the tungsten oxide region in the second memory layer structure.

The structures and methods of the present invention are disclosed in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims. These and other embodiments, features, aspects, and advantages of the technology can be understood with regard to the following description, appended claims and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with respect to specific embodiments thereof, and reference will be made to the drawings, in which:

FIG. 1 is a schematic diagram of a bistable resistance random access memory array in accordance with the present invention.

FIGS. 2 is a simplified block diagram of an integrated circuit of the bistable resistance random access memory architecture according to an embodiment of the present invention.

FIG. 3 is a simplified process diagram illustrating a reference step in the manufacturing of the bistable resistance random access memory with a standard tungsten plug or via process in a single memory cell in accordance with the present invention.

FIG. 4 is a process diagram showing a next step in the manufacturing of the bistable resistance random access memory with a recess etch of a tungsten plug structure in accordance with the present invention.

FIG. 5 is a process diagram illustrating the formation of a tungsten oxide region with a dielectric spacer etch, a dry dioxide plasma etch and a wet strip in accordance with the present invention.

FIG. 6 is a process diagram showing a next step in the manufacturing of the bistable resistance random access memory with the formation of a bit line in accordance with the present invention.

FIG. 7 is a process diagram showing a next step in the manufacturing of the bistable resistance random access memory with connections to select devices in accordance with the present invention.

FIG. 8 is a process diagram illustrating a first embodiment of a memory structure with multi-memory layers and a tungsten oxide region for multilevel-cell functions in accordance with the present invention.

FIG. 9 is a process diagram illustrating a second embodiment of a memory structure with multi-memory layers and a tungsten oxide region for multilevel-cell functions in accordance with the present invention.

FIG. 10 is a process diagram illustrating a third embodiment of a memory structure with multi-memory layers and a tungsten oxide region for multilevel-cell functions in accordance with the present invention.

FIG. 11 is a graph illustrating an example of the multilevel-cell control of read currents for the first embodiment in the memory structures with the tungsten oxide region serving as an active area in accordance with the present invention.

DETAILED DESCRIPTION

A description of structural embodiments and methods of the present invention is provided with reference to FIGS. 1-11 . It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments but that the invention may be practiced using other features, elements, methods and embodiments. Like elements in various embodiments are commonly referred to with like reference numerals.

Various embodiments are directed at three-dimensional memory structures and a manufacturing method for memory, such as nonvolatile embedded memory implementing programmable resistance RAM. Examples of resistance device RAM are resistance memory (RRAM), polymer memory, and phase change memory (PCRAM).

FIG. 1 is a schematic illustration of a bistable resistance random access memory array 100, which can be implemented as described herein. In the schematic illustration of FIG. 1, a common source line 128, a word line 123 and a word line 124 are arranged generally parallel in the Y-direction. Bit lines 141 and 142 are arranged generally parallel in the X-direction. Thus, a Y-decoder and a word line driver in a block 145 are coupled to the word lines 123, 124. An X-decoder and a set of sense amplifiers in block 146 are coupled to the bit lines 141 and 142. The common source line 128 is coupled to the source terminals of access transistors 150, 151, 152 and 153. The gate of access transistor 150 is coupled to the word line 123. The gate of access transistor 151 is coupled to the word line 124. The gate of access transistor 152 is coupled to the word line 123. The gate of access transistor 153 is coupled to the word line 124. The drain of access transistor 150 is coupled to the bottom electrode member 132 for sidewall pin memory cell 135, which has top electrode member 134 and bottom electrode member 132. The top electrode member 134 is coupled to the bit line 141. It can be seen that the common source line 128 is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic. In other embodiments, the access transistors can be replaced by diodes, or other structures for controlling current flow to selected devices in the array for reading and writing data.

FIG. 2 is a simplified block diagram of an integrated circuit 200 of an RRAM architecture according to an embodiment of the present invention. The integrated circuit 275 includes a memory array implemented using sidewall active pin bistable resistance random access memory cells on a semiconductor substrate. A row decoder 261 is coupled to a plurality of word lines 262, and arranged along rows in the memory array 260. A pin decoder 263 is coupled to a plurality of bit lines 264 arranged along pins in the memory array 260 for reading and programming data from the sidewall pin memory cells in the memory array 260. Addresses are supplied on a bus 265 to a pin decoder 263 and a row decoder 261. Sense amplifiers and data-in structures in a block 266 are coupled to the pin decoder 263 via a data bus 267. Data is supplied via the data-in line 271 from input/output ports on the integrated circuit 275 or from other data sources internal or external to the integrated circuit 275, to the data-in structures in the block 266. In the illustrated embodiment, other circuitry is included on the integrated circuit, such as a general-purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the thin film bistable resistance random access memory cell array. Data is supplied via the data-out line 272 from the sense amplifiers in block 266 to input/output ports on the integrated circuit 275, or to other data destinations internal or external to the integrated circuit 275.

A controller utilized in this example using bias arrangement state machine 269 controls the application of bias arrangement supply voltages 268, such as read, program, erase, erase verify and program verify voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.

FIG. 3 is a simplified process diagram 300 illustrating a reference step in the manufacturing of the bistable resistance random access memory with a standard tungsten plug (W-plug) or a via process in a single memory cell. A via or contact hole is formed with dielectric members 310, 312 and barrier material 320. A tungsten material 330 is filled into the via disposed between the barrier material 320. A polishing technique such as chemical-mechanical polishing (CMP) or etch back is performed on a surface 340 after the deposition of the tungsten material 330. In one embodiment, the critical dimension (CD) of a tungsten plug (W-plug) 330 complies with the following design rules: for 0.13 μm technology node, the via or contact of W-plug CD ranges from 0.1 μm to 0.25 μm.

FIG. 4 is a process diagram 400 showing a next step in the manufacturing of the bistable resistance random access memory that carries out a recess etch of a tungsten plug member 430. The recess etch process of the tungsten plug member 430 may be carried out by SF6 dry etch, or other chemistries including Ar and/or N2 and/or O2. The aspect ratio of the recess etch is about 1, e.g., the critical dimension of 200 nm has the depth of about 200 nm. After the tungsten recess etch, a barrier isotropic etch process etches away a portion of the Ti or TiN from the barrier 320 to form a barrier member 420. A suitable etching technique for the barrier isotropic etch is by dry etch with chemistries of chlorine (Cl₂) and/or trichloroborane (BCl₃) and/or others, such as Argon (Ar). A wet clean with a solvent, such as EKC265 or others, can be used to remove the polymer residue during the barrier etch.

FIG. 5 is a process diagram 500 illustrating the formation of a tungsten oxide (WOx) with a dielectric spacer etch, a dry dioxide plasma etch and a wet strip. In the dielectric spacer etch, the process involves depositing a dielectric film and etching dielectric spacers 510, 512. The dielectric film is deposited over the tungsten plug member 430 with a chemical vapor deposition (CVD) technique. Suitable materials for implementing the dielectric film include silicon dioxide SiO₂, silicon nitride SiN or silicon oxynitride SiON. The dielectric film possesses the characteristic of a conformal property. A typical thickness of the dielectric film ranges from about 50 nm to about 100 nm. The dielectric film is deposited over the tungsten plug member 430, which is then etched to form dielectric spacers 510, 512. Using a dry etch by chemistries of CF4 and/or C4F8, in which the etching stops on the top surface of the tungsten plug member 430 with a slight tungsten recess to ensure that there is sufficient over-etching, is suitable dielectric spacer etch.

After the dielectric spacer etch, a WOx member 520 is formed with an oxygen (O₂) plasma dry strip, Embodiments of the oxygen plasma dry strip process include a pure O₂ gas plasma chemistry, or mixed chemistries for O₂ plasma such as O₂/N₂ or O₂/N₂/H₂. Suitable mix chemistries for O₂ plasma include O₂/N₂, O₂/N₂/H₂, or pure O₂ gas with a plasma, such as direct plasma, magnetic field enhance reactive ion plasma, or down-stream plasma. Exemplary parameters of a down-stream plasma include a pressure of about 1500 mtorr, a power of about 1000W, an O₂/N₂ flow of about 3000 sccm/200 sccm, a temperature of about 150° C., and a time duration of about 400 seconds.

A wet strip is carried out to remove polymer residue that is generated during dielectric spacer etch process. A suitable chemical for the wet strip is aqueous organic mixtures such as solvent of EKC265 or other types of the same or similar mixtures. The wet strip step may be optional if the dry O₂ plasma is sufficiently over-stripped.

FIG. 6 is a process diagram 600 showing a next step in the manufacturing of the bistable resistance random access memory with the formation of a bit line. An optional step is depositing a barrier layer 610 over the dielectric members 310, 312 and the dielectric spacers 510, 512 by using chemical vapor deposition process. Titanium nitride (TiN) or tantalum nitride (TaN) can be selected, for example, as a suitable material for implementing the barrier layer 610. The deposition of the barrier layer 610 may be an optional step if there is sufficient adhesion when a bit line layer 620 is deposited.

The bit line layer 620 is deposited over the barrier layer 6 1 0 assuming that the optional step of the barrier layer deposition is executed. If the deposition of the barrier layer 610 is skipped, the bit line layer 620 is deposited directly over the dielectric members 310, 312 and the dielectric spacers 510, 512. Suitable materials for implementing the bit line layer 620 include poly-Si, W, Cu, or AlCu. If poly-Si is selected for implementing the bit line layer 620, a heavy doping may be required to decrease the amount of resistance.

Process diagram 600 represents a simplified memory cell with a memory layer structure 850 and a top bit line 710, which includes either just the bit line layer 620 or a combination of the bit line layer 620 and the barrier layer 610, with the dielectric spacers 510, 512, and dielectric members 310, 312. FIG. 7 is a process diagram 700 showing a next step in the manufacturing of the bistable resistance random access memory with connections to select devices. The memory layer structure 850 is coupled to a p-n diode 720, which is in turn coupled to a bottom bit line 730. Suitable materials for implementing the bottom bit line layer 730 include poly-Si, W, Cu, or AlCu.

FIG. 8 is a process diagram illustrating a first embodiment of a memory structure 800 with multi-memory layers and a tungsten oxide region for multilevel-cell functions. In this embodiment, the memory structure 800 includes two memory layers, a first memory layer 810 and a second memory layer 850. The first memory layer 810 is coupled to an n-p diode 820, which is in turn coupled to a bottom bit line 830. The first memory layer structure 810 comprises a tungsten oxide region 816, a tungsten plug member 812 and a barrier member 814. The tungsten oxide region 816 extends into a principle surface of the tungsten plug member 812 or a first electrode 812. The barrier member 814 surrounds the tungsten plug member 812.

The tungsten oxide region 816 in the first memory layer structure 810 electrically contacts a second bit line 860 or a second electrode associated with the first memory layer structure 810. The second bit line 860 includes just the bit line 730, or a combination of the bit line 730 and the barrier layer 862. The second bit line 860 in this embodiment serves a dual purpose, first as a top bit line associated with the first memory layer structure 810 and second as a bottom bit line associated with the second memory layer structure 850.

The second bit line 860 is electrically coupled to the p-n diode 720 on top, which is in turn electrically coupled to the second memory layer structure 850. The second memory layer structure 850 comprises the tungsten oxide region 520, the tungsten plug member 430 and the barrier member 820. The tungsten oxide region 520 extends into a principle surface of the tungsten plug member or a first electrode 430. The barrier member 8420 surrounds the tungsten plug member 430.

The tungsten oxide region 520 in the second memory layer structure 850 electrically contacts the top bit line or a third bit line 710, or a second electrode associated with second first memory layer structure 710. The third bit line 710 includes just the bit line 620, or a combination of the bit line 620 and the barrier layer 610.

The critical dimension of an active area (i.e., the tungsten oxide region 520) is determined by the size of the tungsten plug member 430 and the thickness of the dielectric spacers 510, 512. In this embodiment, the critical dimension of the tungsten oxide region 520 is less than the size of the tungsten plug member 430. The critical dimension of the tungsten oxide region 520 is also less than the size of the p-n diode 720. The relationship between the critical dimension of the tungsten oxide region 520, the critical dimension of the tungsten plug member 430, and the thickness of the p-n diode 720 can be represented mathematically as follows:

d _(A) ≈d _(W)−2*t _(D)

where the parameter d_(A) represents the critical dimension of the tungsten plug 520, the parameter d_(W) represents the critical dimension of the plug structure member 430, and the parameter t_(D) represents the critical dimension of the p-n diode 720. The critical dimension of the p-n diode 730 is larger than the critical dimension of the tungsten oxide region 520, represented mathematically as d_(D)>d_(A). In one embodiment, for example, the critical dimension of the p-n diode 730 is about ten times the critical dimension of the tungsten oxide region 520, represented mathematically as d_(D)>10*d_(A). Other exemplary critical dimensions for the parameters describe above are, but are not limited to, the critical dimension of the p-n diode d_(D)−0.3 μm, the critical dimension of the tungsten plug member d_(W)=0.3 μm, the critical dimension of the thickness of the dielectric spacer t_(D)=135 mm, and the critical dimension of the tungsten oxide region d_(A)=30 nm.

FIG. 9 is a process diagram illustrating a second embodiment of a memory structure 900 with multi-memory layers and a tungsten oxide region for multilevel-cell functions. The memory structure 900 comprises a first memory layer structure 910 and a second memory layer structure 950. The first memory layer structure 910 includes the tungsten oxide region 816 extending from a principal surface of a tungsten plug structure 920 surrounded by a barrier member 922. The second memory layer structure 950 includes the tungsten oxide region 520 overlying on a principal surface of a tungsten plug structure 960 surrounded by a barrier member 962. Each of the tungsten plug structures 920, 960 has a dimension that is sufficiently small so that the dielectric step as described with respect to FIG. 5 can be skipped during the manufacturing of the memory structure 900. The critical dimension of the size of the tungsten plug structure 920, 920 is about the same size as the critical dimension for the respective active area, i.e. the tungsten oxide region 816 and the tungsten oxide region 520. A second bit line 980, disposed above the tungsten oxide region 816 and below the p-n diode 430, has a barrier member 982 with a dimension that is similar to a dimension of the bit line member 720.

FIG. 10 is a process diagram illustrating a third embodiment of a memory structure 1000 with multi-memory layers and a tungsten oxide region for multilevel-cell functions. The memory structure 1000 comprises a first memory layer structure 1010 and a second memory structure 1050. The first memory layer structure 1010 includes the tungsten oxide region 816, a tungsten plug structure having a first plug portion 1020 and a second plug portion 1022, and the outer walls of the second plug are surrounded by a barrier member 1024. The critical dimension of the first plug portion 1062 is similar to the critical dimension of the active area, i.e. tungsten oxide region 520. The tungsten oxide portion 816 extends from a principle surface or a top surface of the first plug portion 1020. The first plug portion 1020 has a dimensional value which is less than the second plug portion 1022.

The first plug portion 1020 and the second plug portion 1022 can be manufactured using a self-align process or a non-self-align process. For the non-self-align process, two photolithographic processes are typically employed to define the tungsten plug structure with two different critical dimensions, a first critical dimension for the first plug portion 1020 and a second critical dimension for the second plug portion 1022.

The self-align process involves a step to reduce a cross-section of a part of the interlayer contacts. This reduction process is performed in some embodiments by forming dielectric structures at least partly covering the interlayer contacts, and reducing a cross-section of a part of the interlayer contacts by removing material from a part of the interlayer contacts uncovered by the dielectric structures. One example of reducing the cross-section is performed as follows. A dielectric layer is exposed by the interlayer contacts, by removing another dielectric layer at least by the interlayer contacts. A new dielectric layer is formed at least partly covering the interlayer contacts. Only part of the new dielectric layer covering the interlayer contacts is removed, thereby leaving dielectric structures at least partly covering the interlayer contacts. One example of removing the new material is by wet etching part of the new dielectric layer for a duration, which controls a critical dimension of the interlayer contacts achieved by reducing the cross-section. A chemical mechanical polishing (CMP) process planarizes the surface and opens the contact portions which are covered by the formation of dielectric structures. O₂ plasma oxidation is used to form the tungsten oxide region 520 and the tungsten oxide region 816. For additional information on the self-align process and the chemical mechanical process, see U.S. patent application Ser. No. 11/426,213 entitled “Programmable Resistive RAM and Manufacturing Method”, filed on 23 Jun. 2006, owned by the assignee of this application and incorporated by reference as if fully set forth herein.

FIG. 11 is a graph 1100 illustrating an example of the multilevel-cell control of read currents for the first embodiment in the memory structures 800 with the tungsten oxide region 520 serving as an active area. The graph 1110 is depicted with the x-axis 1112 representing the amount of electrical current, and the y-axis representing the read time 1114. The active area, i.e. the tungsten oxide region 520, is operable in 4 states (2 bits/cell) for each memory layer as defined by the level of a read current. The four different states in the multilevel-cell control are determined by the amount of read current. A first data line 1120 represents a first state (the “0,” state), a second data line 1122 represents a second state (the “1” state), a third data line 1124 represents a third state (the “−1” state), and the fourth data line represents a fourth state (the “−2” state).

The highest read current state requires a high current to conduct a read operation. A reduction in the active area, for example, to be 1/10 size can decrease the current density loading of a diode to around lower than 103 A/cm2. In one embodiment, the read currents for each of the four states are: 4 nA, 40 nA, 0.4 μA, and 2 μA. The present invention can be extended to further divide the read current windows for a memory cell that has multiple bits, such as 4 bits in a memory cell with 16 representative states.

The following are short summaries describing four types of resistive memory material suitable for implementing a memory structure of the present invention. A first type of memory material suitable for use in embodiments is colossal magnetoresistance (“CMR”) material, such as Pr_(x)Ca_(y)MnO₃ where x:y=0.5:0.5, or other compositions with x: 0˜1; y: 0˜1. CMR material that includes Mn oxide is alternatively used.

An exemplary method for forming CMR material uses PVD sputtering or magnetron-sputtering method with source gases of Ar, N₂, O₂, and/or He, etc, at the pressure of 1 mTorr 100 mTorr. The deposition temperature can range from room temperature to ˜600° C., depending on the post-deposition treatment condition. A collimater with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several tens of volts to several hundreds of volts is also used. On the other hand, the combination of DC bias and the collimater can be used simultaneously. A magnetic field of several tens of Gauss to as much as a Tesla (10,000 Gauss) may be applied to improve the magnetic crystallized phase.

A post-deposition annealing treatment in vacuum or in an N₂ ambient or O₂/N₂ mixed ambient is optionally used to improve the crystallized state of CMR material. The annealing temperature typically ranges from 400° C. to 600° C. with an annealing time of less than 2 hours.

The thickness of CMR material depends on the design of the cell structure. The CMR thickness of 10 nm to 200 nm can be used for the core material. A buffer layer of YBCO (YBaCuO₃, which is a type of high temperature superconductor material) is often used to improve the crystallized state of CMR material. The YBCO is deposited before the deposition of CMR material. The thickness of YBCO ranges from 30 nm to 200 nm.

A second type of memory material is two-element compounds, such as Ni_(x)O_(y); Ti_(x)O_(y); Al_(x)O_(y); W_(x)O_(y); Zn_(x)O_(y); Zr_(x)O_(y); Cu_(x)O_(y); etc, where x:y=0.5:0.5, or other compositions with x: 0˜1; y: 0˜1. An exemplary formation method uses a PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N₂, O₂, and/or He, etc. at the pressure of 1 mTorr 100 mTorr, using a target of metal oxide, such as Ni_(x)O_(y); Ti_(x)O_(y); Al_(x)O_(y); W_(x)O_(y); Zn_(x)O_(y); Zr_(x)O_(y); Cu_(x)O_(y); etc. The deposition is usually performed at room temperature. A collimater with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several tens of volts to several hundreds of volts is also used. If desired, the combination of DC bias and the collimater can be used simultaneously

A post-deposition annealing treatment in vacuum or in an N₂ ambient or O₂/N₂ mixed ambient is optionally performed to improve the oxygen distribution of metal oxide. The annealing temperature ranges from 400° C. to 600° C. with an annealing time of less than 2 hours.

An alternative formation method uses a PVD sputtering or magnetron-sputtering method with reactive gases of Ar/O₂, Ar/N₂/O₂, pure O₂, He/O₂, He/N₂/O₂ etc. at the pressure of 1 mTorr˜100 mTorr, using a target of metal oxide, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The deposition is usually performed at room temperature. A collimater with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several tens of volts to several hundreds of volts is also used. If desired, the combination of DC bias and the collimator can be used simultaneously.

A post-deposition annealing treatment in vacuum or in an N₂ ambient or O₂/N₂ mixed ambient is optionally performed to improve the oxygen distribution of metal oxide. The annealing temperature ranges from 400° C. to 600° C. with an annealing time of less than 2 hours.

Yet another formation method uses oxidation by a high temperature oxidation system, such as a furnace or a rapid thermal pulse (“RTP”) system. The temperature ranges from 200° C. to 700° C. with pure O₂ or N₂/O₂ mixed gas at a pressure of several mTorr to 1 atm. The time can range several minutes to hours. Another oxidation method is plasma oxidation. An RF or a DC source plasma with pure O₂ or Ar/O₂ mixed gas or Ar/N₂/O₂ mixed gas at a pressure of 1 mTorr to 100 mTorr is used to oxidize the surface of metal, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The oxidation time ranges several seconds to several minutes. The oxidation temperature ranges from room temperature to 300° C., depending on the degree of plasma oxidation.

A third type of memory material is a polymer material, such as TCNQ with doping of Cu, C₆₀, Ag etc. or PCBM-TCNQ mixed polymer. One formation method uses evaporation by thermal evaporation, e-beam evaporation, or molecular beam epitaxy (“MBE”) system. A solid-state TCNQ and dopant pellets are co-evaporated in a single chamber. The solid-state TCNQ and dopant pellets arc put in a W-boat or a Ta-boat or a ceramic boat. A high electrical current or an electron-beam is applied to melt the source so that the materials are mixed and deposited on wafers. There are no reactive chemistries or gases. The deposition is performed at a pressure of 10⁻⁴ Torr to 10⁻¹⁰ Torr. The wafer temperature ranges from room temperature to 200° C.

A post-deposition annealing treatment in vacuum or in an N₂ ambient is optionally performed to improve the composition distribution of polymer material. The annealing temperature ranges from room temperature to 300° C. with an annealing time of less than 1 hour.

Another technique for forming a layer of polymer-based memory material is to use a spin-coater with doped-TCNQ solution at a rotation of less than 1000 rpm. After spin-coating, the wafer is held (typically at room temperature or temperature less than 200° C.) for a time sufficient for solid-state formation. The hold time ranges from several minutes to days, depending on the temperature and on the formation conditions.

A fourth type is chalcogenide material, such as Ge_(x)Sb_(y)Te_(z) where x:y:z=2:2:5, or other compositions with x: 0˜5; y: 0˜5; z: 0˜10. GeSbTe with doping, such as N—, Si—, Ti—, or other element doping is alternatively used.

An exemplary method for forming chalcogenide material uses PVD-sputtering or magnetron-sputtering method with source gas(es) of Ar, N₂, and/or He, etc. at the pressure of 1 mTorr˜100 mTorr. The deposition is usually performed at room temperature. A collimater with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several tens of volts to several hundreds of volts is also used. On the other hand, the combination of DC bias and the collimater can be used simultaneously.

A post-deposition annealing treatment in vacuum or in an N₂ ambient is optionally performed to improve the crystallize state of chalcogenide material. The annealing temperature typically ranges from 100° C. to 400° C. with an annealing time of less than 30 minutes. The thickness of chalcogenide material depends on the design of the cell structure. In general, a chalcogenide material with thickness of higher than 8 nm can have a phase change characterization so that the material exhibits at least two stable resistance states.

Embodiments of the memory cell in the bistable EM 300 may include phase change based memory materials, including chalcogenide based materials and other materials, for the first resistance random access memory layer 3 10 and the second resistance random access memory layer 320. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of. Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as Te_(a)Ge_(b)Sb_(100−(a+b)). One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky '112 patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge₂Sb₂Te₅, GeSb₂Te₄ and GeSb₄Te₇, (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v.3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given In Ovshinsky '112 patent at columns 11-13, which examples are hereby incorporated by reference.

Phase change alloys can be switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.

Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In following sections of the disclosure, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a PCRAM described herein is Ge₂Sb₂Te₅.

Other programmable resistive memory materials may be used in other embodiments of the invention, including N₂ doped GST, Ge_(x)Sb_(y), or other material that uses different crystal phase changes to determine resistance; Pr_(x)Ca_(y)MnO₃, PrSrMnO₃, ZrO_(x), WO_(x), TiO_(x), AlO_(x), or other material that uses an electrical pulse to change the resistance state; 7,7,8,8-tetracyanoquinodimethane (TCNQ), methanofullerene 6,6-phenyl C61-butyric acid methyl ester (PCBM), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C₆₀-TCNQ, TCNQ doped with other metal, or any other polymer material that has bistable or multi-stable resistance state controlled by an electrical pulse.

For additional information on the manufacture, component materials, use and operation of phase change random access memory devices, see U.S. patent application Ser. No. 11/155,067 entitled “Thin Film Fuse Phase Change RAM and Manufacturing Method”, filed on 17 Jun. 2005, owned by the assignee of this application and incorporated by reference as if fully set forth herein.

The invention has been described with reference to specific exemplary embodiments. Various modifications, adaptations, and changes may be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded as illustrative of the principles of this invention rather than restrictive, the invention is defined by the following appended claims. 

1. A memory structure having multiple memory layers, comprising: a first memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode and electrically connecting between the first electrode and a second electrode, the first electrode having a dimension that is substantially similar to a dimension of the tungsten oxide region; and a second memory layer structure, coupled to the first memory layer structure, having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode in the second memory layer structure and electrically connecting between the first electrode in the second memory layer structure and a second electrode in the second memory layer structure, the first electrode in the second memory layer structure having a dimension that is substantially similar to a dimension of the tungsten oxide region in the second memory layer structure.
 2. The memory structure of claim 1, wherein the tungsten oxide region provides a multilevel function in the operation in the first memory layer.
 3. The memory structure of claim 1, wherein the first electrode comprises a plug structure filled with tungsten.
 4. The memory structure of claim 3, further comprising a barrier material surrounding the outer surface of the tungsten in the plug structure.
 5. The memory structure of claim 1, further comprising an n-p diode electrically coupled to the first electrode in the first memory layer structure.
 6. The memory structure of claim 5, further comprising a first bit line electrically coupled to the p-n diode.
 7. The memory structure of claim 1, further comprising a p-n diode electrically coupled to the first electrode in the second memory layer structure.
 8. The memory structure of claim 7, further comprising a second bit line electrically coupled between the tungsten oxide region in the first memory layer structure and the p-n diode.
 9. The memory structure of claim 8, further comprising a third bit line electrically coupled to the tungsten oxide region in the second memory layer structure.
 10. A memory structure having multiple memory layers, comprising: a first memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending into the principle surface of the first electrode and electrically connecting between the first electrode and a second electrode; and a second memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending into the principle surface of the first electrode in the second memory layer structure and electrically connecting between the first electrode in the second memory layer structure and a second electrode in the second memory layer structure.
 11. The memory structure of claim 10, wherein the tungsten oxide region provides a multilevel function in the operation in the first memory layer.
 12. The memory structure of claim 10, wherein the first electrode comprises a plug structure filled with tungsten.
 13. The memory structure of claim 12, further comprising a barrier material surrounding the outer surface of the tungsten in the plug structure.
 14. The memory structure of claim 10, further comprising an n-p diode electrically coupled to the first electrode in the first memory layer structure.
 15. The memory structure of claim 14, further comprising a first bit line electrically coupled to the p-n diode.
 16. The memory structure of claim 10, further comprising a p-n diode electrically coupled to the first electrode in the second memory layer structure.
 17. The memory structure of claim 16, further comprising a second bit line electrically coupled between the tungsten oxide region in the first memory layer structure and the p-n diode.
 18. The memory structure of claim 17, further comprising a third bit line electrically coupled to the tungsten oxide region in the second memory layer structure.
 19. A memory structure having multiple memory layers, comprising: a first memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode and electrically connecting between the first electrode and a second electrode, the first electrode including a plug structure having a first plug portion having a dimension and a second plug portion having a dimension, the dimension of the first plug portion having a smaller value than the dimension of the second plug portion, the tungsten oxide region having a dimension that is substantially similar to the dimension of the first electrode; and a second memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode in the second memory layer structure and electrically connecting between the first electrode in the second memory layer structure and a second electrode in the second memory layer structure, the first electrode in the second memory layer structure including a plug structure having a first plug portion having a dimension and a second plug portion having a dimension, the dimension of the first plug portion in the plug structure of the second memory layer structure having a smaller value than the dimension of the second plug portion in the plug structure of the second memory layer structure, the first electrode in the second memory layer structure having a first dimension that is substantially similar to a first dimension of the tungsten oxide region in the second memory layer structure.
 20. The memory structure of claim 19, wherein the first plug portion is self-aligned with the second plug portion.
 21. The memory structure of claim 20, wherein the first plug portion is not self-aligned with the second plug portion.
 22. A method for manufacturing a memory device, comprising: forming a plug structure with a plug material surrounded by a barrier material and disposed between dielectric members; etching a top portion of the plug material and the barrier material with a dry etch using a first chemistry followed by a wet recess etch with a second chemistry; and forming dielectric spacers over a principle surface of the etched plug material; forming a tungsten oxide region entering the principle surface of the etched plug material by a dry oxygen plasma strip; and forming a bit line into the dielectric spacers and over the tungsten oxide region.
 23. The method of claim 22, wherein the dry etch with the first chemistry comprises a SF6 dry etch.
 24. The method of claim 22, wherein the recess etching with the second chemistry comprises a barrier isotropic etch using chlorine, trichloroborane or argon.
 25. The method of claim 22, wherein the dry oxygen plasma strip comprises mixed chemistries of O₂/N₂ or O₂/N₂/H₂.
 26. The method of claim 22, wherein the dry oxygen plasma strip comprises pure oxygen gas with a plasma including a direct plasma, a magnetic field enhanced reactive ion plasma, or a down-stream plasma.
 27. The method of claim 22, wherein the bit line comprises a bit line overlying a barrier layer. 